# Electrical Engineering Questi

A. Convert the system data to per unit on a 100 MVA base. Use the voltage of generator 1 as the base voltage. Present your results in a table.

B. Develop the YBus matrix for the system, with the transformer phase shifts included.

C. Build the system using PowerWorld Simulator including the transformer phase shifts. Set your slack bus as Bus 1, and set the angle to be 30 degrees. Solve the power flow, and compare your results with the values given in table
2. Treat this as your base case system. Display the same data fields for all subsequent power flow results.

D. Compare the YBus matrix obtained from PowerWorld with the one you developed in part B.

E. Lower Pgen2 to 0.7 per unit. Try lowering it to 0.5 per unit. What do you think would happen if the generator was taken off line? This is not the same as lowering Pgen2 to zero. Comment on your results especially the voltage magnitudes and the total losses. Explain what would be different if you simply set Pgen2 = 0 in the simulation and how this will impact the results.

F. Starting from the initial operating condition of part A., change the voltage setpoint of generator 1 in 0.01 pu steps until all of the bus voltages are greater than 0.95 pu and list the power flow results.

G. Starting from the initial operating condition of part A., add a shunt capacitor at BUS 3 and determine the Mvar rating to bring all of the bus voltages up to at least 0.95 pu. What is the actual Mvar supplied by the capacitor? List your power flow results.

H. Repeat part G. with the capacitor instead added at BUS 4. Which case requires a least Mvar rating for the capacitor? List your power flow results.

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# Electrical Engineering Questi

In this homework, you are to implement the following designs on the Xilinx FPGA board you have been given. This homework includes 2 state machines.

A) In this question, we want to show specific patterns on the board’s LEDs periodically. The circuit has 2 inputs (A, B) fed by the two rightmost switches of the board (SW0, SW1, respectively). Based on the values on these inputs, the lights should turn on/off periodically according to the patterns shown in Table 1. Switch1, Switch 0 Light Patterns (1: Turn on, 0:Turn off)

00 P0: 0 0 1 1 0 0 1 1 P1: 1 1 0 0 1 1 0 0 01 P2: 0 0 0 0 0 0 0 1 P3: 0 0 0 0 0 0 1 0 P4: 0 0 0 0 0 1 0 0 P5: 0 0 0 0 1 0 0 0 P6: 0 0 0 1 0 0 0 0 P7: 0 0 1 0 0 0 0 0 P8: 0 1 0 0 0 0 0 0 P9: 1 0 0 0 0 0 0 0 10 P9: 1 0 0 0 0 0 0 0 P8: 0 1 0 0 0 0 0 0 P7: 0 0 1 0 0 0 0 0 P6: 0 0 0 1 0 0 0 0 P5: 0 0 0 0 1 0 0 0 P4: 0 0 0 0 0 1 0 0 P3: 0 0 0 0 0 0 1 0 P2: 0 0 0 0 0 0 0 1 11 PA: 1 0 0 0 0 0 0 1 PB: 0 0 0 1 1 0 0 0

Table 1

NOTE 1: As the embedded clock in the board is too fast to follow by eye, please feed your state machine by a slow clock. You can design a 27-bit counter (similar to what you did in Hw3) and use the MSB of the counter output to feed your state machine clock signal.

NOTE 2: Please use the LED7 to LED0 to show the output patterns. 2

B) Implement the following state machine you designed in the previous homework (5A) on the FPGA board.

➢ A Moore machine whose output gets ‘1’ when either the last inputs are 101 or 1001. NOTE 1:

Please use the central push button (BTNC) on the board as a clock signal for your state machine. In addition, please use SW0 switch (the rightmost switch) to feed the input data bit stream.

NOTE 2: Please demonstrate the results on the LED0 (the rightmost LED).

NOTE 3: To make your clock signal (generated via the central push button) robust (glitch less) you should use a filter. You already have the filter.v from assignment 3. You can instantiate it as below: Filter #(.wd(16), .n(65535), .bound(64000)) uut(.clk(CLK100MHZ),.data_in(BTNC),.data_out(BTNC_Filter));

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